Increased "CW rf delay" to 30 msec, and use this value in new_protocol.c

diff --git a/new_protocol.c b/new_protocol.c
index 499e6cdb7cee892f4d850a87f820f47a0cb3ddea..5b14ec07899e544b3c665f312407fa0b063de562 100644 (file)
--- a/new_protocol.c
+++ b/new_protocol.c
@@ -1282,13 +1282,7 @@ static void new_protocol_transmit_specific() {
     transmit_specific_buffer[10]=cw_keyer_weight; // cw weight
     transmit_specific_buffer[11]=cw_keyer_hang_time>>8;
     transmit_specific_buffer[12]=cw_keyer_hang_time; // cw hang delay
-    //
-    // Measurements with my Anan-7000 show that RF delays up to 20 msec
-    // tend to chop the first dot, and the "rising" envelope at the
-    // beginning of the dot is also not good. This was tested with the
-    // "straight key" option (external keyer attached to CW input jack).
-    //
-    transmit_specific_buffer[13]=30; // rf delay
+    transmit_specific_buffer[13]=cw_keyer_ptt_delay;
 
     transmit_specific_buffer[50]=0;
     if(mic_linein) {

diff --git a/old_protocol.c b/old_protocol.c
index 97fe4aaab9f9b9f5d74f19878ad3aa1d98c2d149..9d67947f67404d71808a5c3a6a9b532d6a48f191 100644 (file)
--- a/old_protocol.c
+++ b/old_protocol.c
@@ -949,7 +949,7 @@ static void process_control_bytes() {
       //underflow/overflow detection.
       //
       // Measured on HL2 software version 7.2:
-      // multiply FIFO value with 32 to get sample cound
+      // multiply FIFO value with 32 to get sample count
       // multiply FIFO value with 0.67 to get FIFO length in milli-seconds
       // Overflow at about 3600 samples (75 msec).
       //
@@ -1996,11 +1996,10 @@ void ozy_send_buffer() {
       case 11:
         // DL1YCF: HermesLite-II only
         // specify some more robust TX latency and PTT hang times
-        // A latency of 40 msec means that we first send two buffers
-        // of TX iq samples (assuming a buffer length of 1024 samples,
-        // that is 21 msec) before HL2 starts TXing. This should be
-        // enough to prevent underflows and leave some head-room
-        // my measurements indicate that the TX FIFO can hold about
+        // A latency of 40 msec means that we first send 1920
+        // TX iq samples before HL2 starts TXing. This should be
+        // enough to prevent underflows and leave some head-room.
+        // My measurements indicate that the TX FIFO can hold about
         // 75 msec or 3600 samples (cum grano salis). 
         output_buffer[C0]=0x2E;
         output_buffer[C3]=20;   // 20 msec PTT hang time, only bits 4:0

diff --git a/radio.c b/radio.c
index 90ea0c07cc77758f33dd47295f95fae2372583c7..3708262564f1707834daae7d5ae8281046bf9474 100644 (file)
--- a/radio.c
+++ b/radio.c
@@ -251,7 +251,7 @@ int cw_keyer_weight=50; // 0-100
 int cw_keyer_spacing=0; // 0=on 1=off
 int cw_keyer_internal=1; // 0=external 1=internal
 int cw_keyer_sidetone_volume=50; // 0-127
-int cw_keyer_ptt_delay=20; // 0-255ms
+int cw_keyer_ptt_delay=30; // 0-255ms
 int cw_keyer_hang_time=500; // ms
 int cw_keyer_sidetone_frequency=800; // Hz
 int cw_breakin=1; // 0=disabled 1=enabled